Background
This effort proposes to determine the viability and performance of running a Reduced Instruction Set Computer Five (RISC-V) soft microprocessor for the next generation space-qualified Field Programmable Gate Array (FPGA). Spacecraft are limited by size, weight, power, and cost (SWAP-C) and today most rely on both FPGAs and discrete microprocessors to meet onboard processing needs. With advances in capacity for radiation-hardened FPGAs, it is now feasible to implement an advanced softcore microprocessor within the FPGA itself. This has potential to reduce part count and simplify the design greatly while making efficient use of FPGA spare capacity. More importantly, a soft-core microprocessor reduces the required SWAP-C.
Figure 1: Development environment
Approach
This research sought to investigate the viability of using various designs of RISC-V software cores in future space flight payloads and missions by exploring possible configurations and establishing a suite of benchmarks to adequately compare these RISC-V configurations to Southwest Research Institute’s current space flight processor offerings. Microsemi’s open-source RV32 cores were tested in four major configurations, and each configuration at three frequencies on a Microsemi MPF-300-Eval-Kit. Cobham-Gaisler NOEL-V cores were tested in three example configurations: EX1 (minimal single core), EX2 (high performance single core), and EX4 (high performance quad core), on a Xilinx Kintex KCU105 Development Board. The benchmarks tested on all cores were Dhrystone 2, Coremark, and Whetstone. The optimization and sizing of benchmark iterations was consistent among the group of Microsemi RV32 cores and the group of NOEL-V cores. The NOEL-V required larger iteration sizes to acquire accurate results at the faster processing speeds. Benchmarks were run first in a low-overhead environment (bare-metal on Microsemi RV32, minimal Real Time Executive for Multiprocessor Systems on NOEL-V), then again with the added overhead of a Buildroot Linux kernel on the NOEL-V cores.
Accomplishments
Microsemi RV32 cores were evaluated first and demonstrated suboptimal bare-metal benchmark performance. Even a minimal EX1 NOEL-V core configuration was shown to yield superior results to a maximally configured Microsemi RV32 core. The NOEL-V high-performance cores achieved benchmark performance on par with several modern RISC-V hardware microprocessors and some legacy Complex Instruction Set Computer (x86) Central Processing Units. The viability of running Linux on a soft-core was verified, including networking, file transfer, benchmarking with overhead, and running dynamically linked programs. The multi-core performance boost of the EX4 NOEL-V was negligible in these applications even with the benchmarks and operating system built with Symmetric Multiprocessing (SMP) enabled and does not justify the increased device utilization for these selected test workloads.